A xe2x80x9ccomputer program listing appendixxe2x80x9d is submitted herewith on a single CD-ROM disc, and duplicate copies thereof are submitted as Copy 1 and Copy 2, the contents of which are expressly incorporated by reference into this specification.
Each of Copy 1 and Copy 2 contains the following files, wherein each file has:
(1) a name of LinfetLOW5, a size of 150,660, bytes, and is written in Mathcad, available from MathSoft Engineering and Education, Inc. 101 Main Street, Cambridge, Mass. 02142.
(2) a name of SatFETMODxe2x80x945, a size of 80,313 bytes, and is written in Mathcad, available from MathSoft Engineering and Education, Inc. 101 Main Street, Cambridge, Mass. 02142.
Silicon-on-insulator (SOI) starting substrate material can be used as an alternative to standard silicon wafers (xe2x80x9cbulk silicon) to produce integrated circuits. The electrical properties such as electron and hole mobilities, surface state densities, fixed charge densities, and surface scattering properties in part determine how well the field effect transistors (FETs) will perform when this starting material is processed into integrated circuits. One method for assessing these starting wafer properties is to build FETs in the material using standard device processes like ion implantation, annealing, oxidation, diffusion, which are costly and time consuming.
An alternative is to use the buried oxide in the SOI structure as a gate oxide, place two electrodes on the Si surface as source and drain contacts, and use this as a xe2x80x9cpseudo-FET.xe2x80x9d Electrical measurements using such pseudo-FETs have been described in, for example, IEEE Electron Device Letters Vol 13, pg 102, 1992, in Electrical Characterization of Silicon-on-Insulator Materials and Devices, Kluwer Academic Publishers, Boston, 1995, and in IEEE Transactions on Electron Devices Vol. XX, pg 1018, 2000. Similar measurements made using mercury electrodes have been described in Proc. 1997 IEEE International SOI Conference, pg 180, and in Electrochemical and Solid State Letters, Vol 2, pg 242, 1999.
However, all the prior art fails to present details on how these test structures are best made, how to account for the parasitic effects which limit their usefulness, how to set the correct voltage conditions for correct measurements, and do not present the complete mathematical analysis needed to obtain the electrical properties. In particular, the electrical behavior of the mercury-based FET (HgFET) differs from previous pseudo-FETS because of the surface treatment with hydrofluoric acid (HF) prior to contacting with the mercury and because of the unusual, part Schottky-like and part ohmic-like behavior of the mercury electrodes. The analysis equations presented in, for example, the IEEE Transactions article and Kluwer Academic Publishers book mentioned above do not take into account many of the parasitic effects and other unusual behavior associated with the HgFET.
Details of the HgFET preparation and measurements have been disclosed in U.S. patent application Ser. No. 09/770,955, filed on Jan. 26, 2001, entitled xe2x80x9cMethod of Determining Electrical Properties of Silicon-on-Insulator Wafersxe2x80x9d by the same inventor which is expressly incorporated herein by reference. However, this docket does not show the detailed procedures and analysis methods for analyzing measurements of these devices, and in particular, does not present an algorithm useable in computer analysis of such measurements. Without such an algorithm, analysis of the HgFET behavior including the parasitics to extract the electrical parameters from such measurements is extremely difficult, very time consuming, and very costly. Using the methods of the present invention overcomes these difficulties, and one detailed example is given for a mathematical algorithm written with MathCad which quickly and accurately extracts the electrical parameters.
Electrical measurements of liquid metal FETs, such as HgFETs, are made in several current-voltage regimes, specifically, the drain voltage is kept fixed at a low voltage and the gate voltage applied to the substrate side of the wafer is varied either in negative polarities (accumulation mode for the dominant p-type substrates) or the positive polarities (inversion mode). A mathematical algorithm is used which xe2x80x9cimportsxe2x80x9d the electrical data either automatically or from a separate computer disk, and analyzes the data including the parasitic factors to extract the electrical parameters of the Si film. This procedure is carried out at different points in time after HF acid surface treatment which is necessary to obtain proper FET behavior. Certain parameters such as low field electron mobility are derived from the measurements at the early time periods, while the hole mobility, flat band condition, doping level, and buried oxide charge are obtained from the later time periods. The interface state density is taken at its minimum value regardless of when this occurs.
In a second procedure, the drain current versus drain voltage behavior is measured for a family of fixed gate voltages on the substrate. This family of data curves is called the saturated region of the FET. A second mathematical algorithm is described which analyzes the data in this second type of behavior to obtain the saturation threshold voltage, saturated mobility and transconductance, the drive current, and the output conductance. As in the first algorithm, the saturation region analysis algorithm may be included in an automated computer-controlled measurement system or used as xe2x80x9cstand-alonexe2x80x9d in which data is imported and analyzed separately.
Examples of detailed algorithms for accomplishing such data analysis are included in the invention.